Delay generation technique in the 8085:

Delay generation technique in the 8085:

There is a lot of the method for the delay generation in the 8085 one of the most commonly used one is with the help of the software. There is nothing complicated in the programming in all the technique same logic is applied so don't worry you will be fine.............

Delay subroutine using the only 8-bit register:

                                         MVI B, COUNT;
                             LOOP: DCR B;
                                         JNZ LOOP;
                                         RET;
calculation of  the count:
The require count is the hex number you want to count. It will be more clear by considering the example.
1) determine maximum delay that can be able to generate using the 8-bit subroutine.
ANS:
 1)
  maximum allowed in the 8-bit register is 255 i.e FF in the hex.

 2)
Total T-state required by the instruction outside the loop:7+10=17
Total T-state required by the instruction inside  the loop: 4 + 10 = 14

Total T-states  = outside + ( inside * count in decimal ) -3
Total T-states  = 17 + ( 14 * 255 ) -3= 3584
3)
suppose that the given clock frequency is 2 Mhz then  time peariod of the one T-state is given as :
        1/2*10^6 = 0.5*10^-6 second = 0.5 microsecond 

4)
hence total delay generate is given as:
3584  *  0.5*10^-6 = 1.792msec

                 

Delay subroutine using the only 16-bit register:

                                LXI B, COUNT ; 

                        UP: DCX B;

                                  MOV A,C;

                                 ORA B;

                                 JNZ UP;

                                 RET;

calculation of  the count:

here we will perform the same step. only remember here maximum count is FFFF i.e 65535 in the decimal.

1) determine maximum delay that can be able to generate using the 16-bit subroutine. 

ANS:

 1)

  maximum allowed in the 16-bit register is 65535 i.e FFFF in the hex.

 2)

Total T-state required by the instruction outside the loop:10+10=20

Total T-state required by the instruction inside  the loop: 6+4+4 + 10 = 24

Total T-states  = outside + ( inside * count in decimal ) -3

Total T-states  = 20 + ( 24 * 65535 ) -3= 1572857

3) 

suppose that the given clock frequency is 2 Mhz then  time peariod of the one T-state is given as :

        1/2*10^6 = 0.5*10^-6 second = 0.5 microsecond 

4) 

hence total delay generate is given as:

1572857  *  0.5*10^-6 = 0.7864 sec

Delay generation using the two 8 bit register:

 MVI B, COUNT1;

LOOP2: MVI C, COUNT2;

              LOOP1: DCR C;

                            JNZ LOOP1;

                             DCR B;

                             JNZ LOOP2

                              RET;

calculation of  the count:

 T-state outside of the loop2 is = P = 7+10 = 17
T-state inside of the loop2 but outside of loop 1 = M = 7 + 4+ 10 = 21
T-state inside theloop1 = N = 4 + 10 = 14

total T-state in the loop1 =A = M + (count2 in decimal * N) -3 
                                        = 21 + (255*14)-3 = 3588
total T-state require in the loop2 = P + (count1 in decimal * A)-3
                                        = 17 +(255*3588)-3 = 914954

 (repeat the above example to find the total delay .....it is similar from this point)

Delay generation using the two 16-bit register:

LXI B, COUNT1;

LOOP2: LXI H, COUNT 2;

               LOOP1: DCX H;

                                MOV A,L;

                                ORA H;

                                JNZ LOOP1;

                                DCX B;

                                MOV A, C;

                                ORA B;

                                JNZ LOOP2;

                                RET; 

 T-state outside of the loop2 is = P = 10+10 =20

T-state inside of the loop2 but outside of loop 1 = M =10+6+4+4+10 = 34

T-state inside theloop1 = N = 24

total T-state in the loop1 =A = M+ (count2 in decimal * N) -3 

                                        = 34+ (65535*24)-3 = 1572871

total T-state require in the loop2 = P + (count1 in decimal * A)-3

                                        = 20 +(65535*1572871)-3 = 103078101002

 (repeat the above example to find the total delay .....it is similar to this point)

 here final answer will be something about the 

   51539.050501 second 

Dealy generation using the one 8-bit and one 16-bit register:

LXI B ,COUNT 1;

LOOP2 : MVI  D, COUNT2;

               LOOP1; DCR D;

                              JNZ LOOP1;

                              DCX B;

                              MOV A,C;

                              ORA B;

                              JNZ LOOP2;

                             RET;

(All the calculation steps are similar as given above ....)